1. Field of the Invention
This invention relates generally to an apparatus and method for measuring electrical properties of a semiconductor wafer.
2. Description of Related Art
The determination of electrical properties of a dielectric on a semiconductor wafer and/or a carrier density profile within the semiconductor wafer is a critical factor in the production of such wafers. Measurements based on capacitance-voltage (CV) or capacitance-time (Ct) techniques, such as measurements of dielectric thickness, oxide charge, threshold voltage, implant dose and carrier profile; measurements based on conductance-voltage (GV) techniques, such as measurement of interface state density; and measurements based on current-voltage (IV) techniques, such as dielectric leakage current and breakdown voltage, are typically accomplished by first fabricating metal or doped polysilicon gates on the dielectric. These gates become part of a metal oxide semiconductor (MOS) structure which is used to make the appropriate CV, Ct, GV or IV measurement. In other words, these gates become permanent gates on the semiconductor wafer, thereby making the semiconductor unfit for normal use. Thus, these semiconductor wafers are used only as monitor or test semiconductor wafers.
Fabrication of the metal or polysilicon gates is time-consuming and costly. It typically involves depositing and forming aluminum metal or polysilicon gates on the dielectric in a manner known in the art.
An alternative to these fabricated gates is described in an article entitled “Vacuum Operated Mercury Probe for CV Plotting and Profiling” by Albert Lederman, Solid State Technology, August 1981, pp. 123-126. This article discloses utilizing mercury contacts for replacing the aluminum or polysilicon gates in CV measurement techniques designed to characterize dielectric and semiconductor properties. The Lederman paper discloses a vacuum operated mercury probe for performing measurements of metal oxide semiconductors, homogeneous semiconductor wafers, non-homogeneous semiconductor wafers, and semiconductor wafers on insulating substrates. Problems may arise utilizing the Lederman mercury probe in that mercury may react chemically with the materials of the wafer under study. Mercury also poses a significant safety problem in its use and mercury sublimes at elevated temperatures when accelerated temperature testing of the semiconductor wafer is desired. Thus, a mercury probe has limited application.
An alternative to fabricated gates or vacuum operated mercury probes is disclosed in U.S. Pat. No. 5,023,561 to Hillard which issued on Jun. 11, 1991 and which is incorporated herein by reference.
The Hillard patent discloses a kinematic probe arm having at one end thereof a probe including a tip having a uniformly flat surface of predetermined dimensions. A probe stand supports the kinematic arm and a chuck supports the semiconductor wafer. The probe stand, the kinematic arm, and the chuck are configured so that a planar contact can be realized between the uniformly flat portion of the tip and the front surface of the dielectric layer of the semiconductor wafer.
When the Hillard patent was filed in the early 1990′s, a typical gate oxide thickness in the semiconductor industry was on the order of hundreds of angstroms. The relatively small planar contact area between the uniformly flat tip of the probe and the outer surface of the dielectric layer on the wafer resulted in a poor capacitance signal-to-noise ratio when applied to these relatively thick oxides. Hence, while the probe having the uniformly flat tip could be utilized for performing CV Ct or GV measurements, this probe was preferably utilized to perform IV measurements.
In contrast, today, gate oxides are very thin, on the order of 1.0-1.5 nm. With these thin oxides, the capacitance signal-to-noise ratio is increased whereby CV, Ct and GV measurements made with conductive pressure contacts can be effectively utilized to characterize gate oxides.
A problem with utilizing the probe disclosed in the Hillard patent for performing CV measurements is the need to grind the tip uniformly flat. Another problem is the need to establish a planar contact between the uniformly flat tip and the outer surface of the dielectric layer of the wafer. The use of a uniformly flat tip to form a planar contact with the outer surface of the dielectric layer is particularly a problem with today's thin oxide layers since a lack of perfect parallelism between the uniformly flat tip and the outer surface of the dielectric layer may result in an edge surrounding the uniformly flat tip damaging the oxide layer.
Another alternative to permanent gates or temporary mercury gates on monitor semiconductor wafers is the use of test structures formed in scribe lines of product semiconductor wafers. More specifically, test structures are formed in scribe lines of the semiconductor wafer during formation of integrated circuits in the semiconductor wafer. In order to test these test structures, the backside of the semiconductor wafer is received on a wafer chuck. A contact is then formed between the test structure and a distal end of a conventional probe that is connected in circuit with a measurement means and the wafer chuck. The measurement means applies a suitable signal to the test structure via the distal end of the probe tip and measures the response of the test structure to the stimulation.
One problem with forming test structures in scribe lines of product semiconductor wafers includes the additional processing steps necessary to form these test structures. Another problem is the need to test these test structures apart from the testing of the integrated circuits formed on the product semiconductor wafer.
It is, therefore, an object of the present invention to avoid or overcome the above problems and others by providing a probe having an improved tip configuration that enables improved measurement of a dielectric layer or a surface a semiconductor wafer. It is another object of the present invention to eliminate the need for lateral movement between the probe and the wafer in order to test various locations of the wafer. It is a further object of the present invention to eliminate the need to use the back surface of the semiconductor wafer for a return contact. It is yet a further object of the present invention to eliminate the need for monitor or test semiconductor wafers and to provide a method for taking CV, Ct, and GV and IV measurements using the scribe lines of product semiconductor wafers without first forming test structures. Still other objects of the present invention will become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.